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Alif Semiconductor /AE302F80F55D5AE_CM55_HE_View /CSI /CSI_PHY_RX

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Interpret as CSI_PHY_RX

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31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 (PHY_RXULPSESC_0)PHY_RXULPSESC_0 0 (PHY_RXULPSESC_1)PHY_RXULPSESC_1 0 (PHY_RXULPSCLKNOT)PHY_RXULPSCLKNOT 0 (PHY_RXCLKACTIVEHS)PHY_RXCLKACTIVEHS

Description

PHY RX Signals Status Register

Fields

PHY_RXULPSESC_0

Lane module 0 has entered the Ultra Low Power mode.
PHY_RXULPSESC_1

Lane module 1 has entered the Ultra Low Power mode.
PHY_RXULPSCLKNOT

Active low. This signal indicates that D-PHY Clock Lane module has entered the Ultra Low Power State.
PHY_RXCLKACTIVEHS

Indicates that D-PHY clock lane is actively receiving a DDR clock.

Links

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Register License

THIS SOFTWARE IS PROVIDED “AS IS”. NO WARRANTIES, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. ALIF SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.

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Register Reference

https://github.com/cmsis-svd/cmsis-svd-data